Role: AI/ML Architect

Location: Mountain View., California (Hybrid) (Locals Preferr

Responsibilities

• Compiler Architecture & Design
• Design and develop a robust compiler architecture that effectively interacts with our NPU
• Implement advanced graph optimizations that incorporate both hardware agnostic and hardware specific enhancements
• Develop and optimize algorithms for tiling and memory management to efficiently utilize the NPU's resources
• Create sophisticated optimization passes for neural network inference and training workloads
• Code Generation & Hardware Integration
• Map high-level operations to optimized library macros and convert them into hardware-level instructions
• Generate and manage DMA commands to facilitate data movement and operation within the hardware ecosystem
• Collaborate with hardware engineers and system architects to ensure seamless integration and maximal performance of the NPU
• Implement efficient scheduling and resource allocation algorithms for concurrent AI workload execution
• Innovation & Technology Leadership
• Stay updated with the latest trends and advancements in compiler technology and machine learning to continuously improve the compiler design
• Lead research initiatives in advanced compilation techniques for AI accelerators
• Drive adoption of cutting-edge optimization strategies and compilation methodologies
• Mentor engineering teams on compiler design principles and best practices

Skills

Must have

General Skills:

• Expert communicator across cultural and team boundaries
• Expertise in motivating teams and fostering a collaborative and productive environment
• Background in managing multiple and competing stakeholder interests; establishing trust, clear roles and responsibilities, and goodwill between partner engineering organizations
• Experience managing cross-functional and/or cross-team projects
• Technical leadership experience with ability to mentor engineering teams
• Strategic thinking capabilities with focus on long-term architectural decisions
• Collaborate and work with multiple teams across geographies and time zones

Required Specialized Skills:

• 12+ years of experience in compiler development or architecture, particularly targeting AI or ML hardware accelerators
• Strong understanding of machine learning algorithms and their computational implications
• Working experience with TVM, IREE, XLA, MLIR or LLVM
• Proficiency in programming languages such as C++ and Python
• Experience with graph optimization techniques and memory management strategies in compilers
• Demonstrated ability to translate high-level functional requirements into detailed technical designs
• Deep knowledge of hardware architecture principles and AI accelerator design concepts
• Proven track record of leading compiler architecture projects from concept to production deployment

Nice to have

Desired Skills:

• Prior experience with NPU hardware
• Knowledge of automotive industry standards and functional safety requirements
• Experience with neural network quantization and optimization techniques
• Background in high-performance computing and parallel processing architectures
• Publications or contributions to open-source compiler projects
• Experience with GenAI tools for accelerated engineering workflows and AI-assisted development practices
• Enthusiasm for adopting innovative AI-augmented development practices and continuous learning in rapidly evolving GenAI technologies

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Responsibilities

• Compiler Architecture & Design
• Design and develop a robust compiler architecture that effectively interacts with our NPU
• Implement advanced graph optimizations that incorporate both hardware agnostic and hardware specific enhancements
• Develop and optimize algorithms for tiling and memory management to efficiently utilize the NPU's resources
• Create sophisticated optimization passes for neural network inference and training workloads
• Code Generation & Hardware Integration
• Map high-level operations to optimized library macros and convert them into hardware-level instructions
• Generate and manage DMA commands to facilitate data movement and operation within the hardware ecosystem
• Collaborate with hardware engineers and system architects to ensure seamless integration and maximal performance of the NPU
• Implement efficient scheduling and resource allocation algorithms for concurrent AI workload execution
• Innovation & Technology Leadership
• Stay updated with the latest trends and advancements in compiler technology and machine learning to continuously improve the compiler design
• Lead research initiatives in advanced compilation techniques for AI accelerators
• Drive adoption of cutting-edge optimization strategies and compilation methodologies
• Mentor engineering teams on compiler design principles and best practices

Skills

Must have

General Skills:

• Expert communicator across cultural and team boundaries
• Expertise in motivating teams and fostering a collaborative and productive environment
• Background in managing multiple and competing stakeholder interests; establishing trust, clear roles and responsibilities, and goodwill between partner engineering organizations
• Experience managing cross-functional and/or cross-team projects
• Technical leadership experience with ability to mentor engineering teams
• Strategic thinking capabilities with focus on long-term architectural decisions
• Collaborate and work with multiple teams across geographies and time zones

Required Specialized Skills:

• 12+ years of experience in compiler development or architecture, particularly targeting AI or ML hardware accelerators
• Strong understanding of machine learning algorithms and their computational implications
• Working experience with TVM, IREE, XLA, MLIR or LLVM
• Proficiency in programming languages such as C++ and Python
• Experience with graph optimization techniques and memory management strategies in compilers
• Demonstrated ability to translate high-level functional requirements into detailed technical designs
• Deep knowledge of hardware architecture principles and AI accelerator design concepts
• Proven track record of leading compiler architecture projects from concept to production deployment

Nice to have

Desired Skills:

• Prior experience with NPU hardware
• Knowledge of automotive industry standards and functional safety requirements
• Experience with neural network quantization and optimization techniques
• Background in high-performance computing and parallel processing architectures
• Publications or contributions to open-source compiler projects
• Experience with GenAI tools for accelerated engineering workflows and AI-assisted development practices
• Enthusiasm for adopting innovative AI-augmented development practices and continuous learning in rapidly evolving GenAI technologies